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Farideh Golshan

from Santa Clara, CA
Age ~60

Farideh Golshan Phones & Addresses

  • 1568 Vista Club Cir #208, Santa Clara, CA 95054
  • 1193 Elena Privada, Mountain View, CA 94040
  • 1555 W Middlefield Rd #63, Mountain View, CA 94043
  • 900 High School Way, Mountain View, CA 94041
  • Houston, TX
  • Austin, TX
  • Andover, MA

Publications

Us Patents

Multiplexer Select Line Exclusivity Check Method And Apparatus

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US Patent:
6581018, Jun 17, 2003
Filed:
Jul 26, 2000
Appl. No.:
09/625522
Inventors:
Farideh Golshan - Mountain View CA
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G01R 2723
US Classification:
702117, 714736
Abstract:
Disclosed herein is a system and method for determining whether multiplexers select lines within a circuit are exclusive of one another. The disclosed invention may be performed in an automated manner on one or more multiplexers within subunit, across subunits, within units, across units, or within entire modules. The method and system employs the application of logical circuit analysis in combination with predefined gate logic to ascertain select line exclusivity in an automated and flexible fashion.

Apparatus For On-Line Circuit Debug Using Jtag And Shadow Scan In A Microprocessor

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US Patent:
6662325, Dec 9, 2003
Filed:
Oct 5, 2000
Appl. No.:
09/680238
Inventors:
Farideh Golshan - Mountain View CA
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G01R 3128
US Classification:
714726, 714727, 714729
Abstract:
A series of secondary or “shadow” storage elements are employed that duplicate, or “shadow”, the information in a circuits core logic primary storage elements. These shadow storage elements are then coupled to form a separate, independently-addressable shadow scan path. The information contained in the primary storage elements is then scanned out via the shadow scan path without altering the primary storage elements using special commands issued from a JTAG controller. This shadow scan system allows a circuit to remain operational while a snapshot of the core logic information is scanned out.

Method For On-Line Circuit Debug Using Jtag And Shadow Scan In A Microprocessor

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US Patent:
6671841, Dec 30, 2003
Filed:
Oct 5, 2000
Appl. No.:
09/680237
Inventors:
Farideh Golshan - Mountain View CA
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G01R 3128
US Classification:
714729
Abstract:
A series of secondary or “shadow” storage elements are employed that duplicate, or “shadow”, the information in a circuits core logic primary storage elements. These shadow storage elements are then coupled to form a separate, independently-addressable shadow scan path. The information contained in the primary storage elements is then scanned out via the shadow scan path without altering the primary storage elements using special commands issued from a JTAG controller. This shadow scan system allows a circuit to remain operational while a snapshot of the core logic information is scanned out.

Internally Generated Vectors For Burnin System

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US Patent:
6675338, Jan 6, 2004
Filed:
Aug 9, 2000
Appl. No.:
09/635996
Inventors:
Farideh Golshan - Mountain View CA
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G01R 313183
US Classification:
714739
Abstract:
Internally generating test vectors on a microchip during a burnin stage allows for better toggle coverage while not requiring external memory. A test access port (TAP) controller which accepts signals from a user and indicates to a linear feedback shift register (LFSR) that the microchip is in the burnin stage. The LFSR then may generate a set of pseudorandom values using a polynomial. The values are then shifted one per clock cycle into the internal scan chain of flips-flops on the chip, which toggles the internal state of the chip. New pseudorandom values are also generated one-by-one during the shift. By using this approach, the internal states of the chip are toggled without the use of an external memory for the burnin system.

Method And Apparatus For Testing And Debugging A Circuit

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US Patent:
6751764, Jun 15, 2004
Filed:
Jul 19, 2001
Appl. No.:
09/909742
Inventors:
Farideh Golshan - Mountain View CA
Sai Vishwanthaiah - Sunnyvale CA
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G01R 3128
US Classification:
714729
Abstract:
A series of secondary or “shadow” storage elements are employed that duplicate, or “shadow”, the information in a circuits core logic shadowed functional registers. These shadow storage elements are then coupled to form a separate, independently-addressable shadow scan path. The information contained in the shadowed functional registers of a circuit is then shifted out via the shadow scan path without altering the shadowed functional registers using special commands issued from a JTAG controller.

Apparatus And Method For Interfacing Boundary-Scan Circuitry With Dtl Output Drivers

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US Patent:
6219812, Apr 17, 2001
Filed:
Jun 11, 1998
Appl. No.:
9/095795
Inventors:
Farideh Golshan - Mountain View CA
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
G01R 3128
US Classification:
714727
Abstract:
A system for coupling a Dynamic Termination Logic (DTL) type output driver to IEEE 1149. 1 boundary-scan circuitry includes a logic circuit that converts the data and output enable signals of the IEEE 1149. 1 specification to test "q_up," "q_dn" and "q25_dn" signals meeting the requirements of the DTL driver. These test q_up, q_dn and q25_dn are selectively provided to the DTL driver during boundary-scan testing of the output driver. In a further refinement, the system also converts functional q_up, q_dn and q25_dn signals provided by the circuit under test to the data and output enable signals of the IEEE 1149. 1 specification. The system allows the widely used IEEE 1149. 1 boundary-scan standard to be used with DTL drivers. The resulting compatibility simplifies the testing and use of the DTL drivers, and provides a new boundary-scan standard for use with DTL drivers that is compliant with the IEEE 1149. 1 standard.

Method For Interfacing Boundary-Scan Circuitry With Linearized Impedance Control Type Output Drivers

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US Patent:
5872796, Feb 16, 1999
Filed:
Jun 30, 1997
Appl. No.:
8/885054
Inventors:
Farideh Golshan - Mountain View CA
Marc E. Levitt - Sunnyvale CA
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
G06F 1100
US Classification:
371 2232
Abstract:
A method for coupling a linear impedance control (LIC) type output driver to IEEE 1149. 1 boundary scan circuitry includes entering a boundary scan load mode to load a test pattern into a chain of boundary scan registers (BSRs). The test pattern includes values corresponding to output enable and data signals according to the IEEE 1149. 1 standard. Then these data and output enable signals from the BSRs are converted into test "q. sub. -- up" and "q. sub. -- dn" signals meeting the requirements of the LIC driver. These test "q. sub. -- up" and "q. sub. -- dn" signals are selectively provided to the LIC driver during boundary scan testing of the LIC driver. In a further refinement, the method enters a boundary scan capture mode to capture the response (i. e. , the functional q. sub. -- up and q. sub.

Boundary-Scan Circuit For Use With Linearized Impedance Control Type Output Drivers

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US Patent:
5892778, Apr 6, 1999
Filed:
Jun 30, 1997
Appl. No.:
8/885012
Inventors:
Farideh Golshan - Mountain View CA
Marc E. Levitt - Sunnyvale CA
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
G01R 3128
US Classification:
371 2232
Abstract:
A circuit for coupling a LIC driver to a IEEE 1149. 1 boundary scan implementation includes a logic circuit that converts the data and oe signals of the IEEE 1149. 1 specification to test "q. sub. -- up" and "q. sub. -- dn" signals meeting the requirements of the LIC driver. These test "q. sub. -- up" and "q. sub. -- dn" signals are selectively provided to the LIC driver during boundary scan testing of the output driver. In a further refinement, the logic circuit also converts functional q. sub. -- up and q. sub. -- dn signals provided by the circuit under test to the data and oe signals of the IEEE 1149. 1 specification. The logic circuit allows the widely used IEEE 1149. 1 boundary scan standard to be used with LIC drivers. The resulting compatibility simplifies the testing and use of the LIC drivers, and provides a new boundary scan standard for use with LIC drivers that is compliant with the IEEE 1149. 1 standard.
Farideh Golshan from Santa Clara, CA, age ~60 Get Report