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Mir B Ghaderi

from Cupertino, CA
Age ~67

Mir Ghaderi Phones & Addresses

  • 10880 Santa Teresa Dr, Cupertino, CA 95014
  • Mountain View, CA
  • Miami, FL
  • Sunnyvale, CA

Publications

Us Patents

Interleaved Pulse-Extended Phase Detector

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US Patent:
7127021, Oct 24, 2006
Filed:
Jul 19, 2002
Appl. No.:
10/199620
Inventors:
Shin Chung Chen - Los Gatos CA,
Roubik Gregorian - Saratoga CA,
Mir Bahram Ghaderi - Cupertino CA,
Vincent Sing Tso - Milpitas CA,
Assignee:
Exar Corporation - Fremont CA
International Classification:
H03D 3/24
US Classification:
375375
Abstract:
A mechanism for dealing with faster clock speeds by increasing the pulse width of the pump-up and pump-down pulses of a Hogge-type phase detector without dividing the clock. In particular, the NRZ data stream is divided into two, interleaved data streams which are provided through two series of flip-flops. By connecting the exclusive-OR gates separately to the two series of flip-flops to generate the pump-up and pump-down pulses, a longer time between transitions can be achieved by having alternate transitions (up and down) used by the two different series of flip-flops. In addition, delay circuits are provided to compensate for the clock-to-data output delay of the flip-flops.

Precision, Temperature Stable Clock Using A Frequency-Control Circuit And Dual Oscillators

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US Patent:
7764131, Jul 27, 2010
Filed:
Sep 23, 2008
Appl. No.:
12/236456
Inventors:
Manu Seth - San Jose CA,
David Brubaker - Los Altos CA,
Andrew McCraith - Orinda CA,
Richard Steven Miller - Los Altos CA,
Mir Bahram Ghaderi - Cupertino CA,
Assignee:
Silicon Labs SC, Inc. - Sunnyvale CA
International Classification:
H03L 1/00
H03K 3/00
US Classification:
331 46, 331 2, 331176, 327298
Abstract:
A frequency-control circuit, which is configured to receive a first signal having a first untuned frequency from a first oscillator, and to alter one or more pulses of the first signal to tune an output frequency of an output clock signal to have an average frequency at the desired target frequency. In some embodiments, the two oscillators of intentionally different frequencies are periodically switched at a duty factor, which is dependent on an absolute temperature, to generate a calibrated, precise, and temperature-stable clock.

Precision, Temperature Stable Clock Using A Frequency-Control Circuit And A Single Oscillator

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US Patent:
7830216, Nov 9, 2010
Filed:
Sep 23, 2008
Appl. No.:
12/236454
Inventors:
Manu Seth - San Jose CA,
David Brubaker - Los Altos CA,
Andrew McCraith - Orinda CA,
Richard Steven Miller - Los Altos CA,
Mir Bahram Ghaderi - Cupertino CA,
Assignee:
Silicon Labs SC, Inc. - Sunnyvale CA
International Classification:
H03K 3/00
US Classification:
331177R, 331176, 331 74, 327160, 327291
Abstract:
A frequency-control circuit, which is configured to receive a first signal having a first untuned frequency from a first oscillator, and to alter one or more pulses of the first signal to tune an output frequency of an output clock signal to have an average frequency at the desired target frequency. In some embodiments, the frequency-control circuit receives a signal from a single oscillator to generate a calibrated, precise, and temperature-stable clock.

Precision, Temperature Stable Clock Using A Frequency-Control Circuit And A Single Oscillator

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US Patent:
8138846, Mar 20, 2012
Filed:
Jun 30, 2010
Appl. No.:
12/803581
Inventors:
Manu Seth - San Jose CA,
David Brubaker - Los Altos CA,
Andrew McCraith - Orinda CA,
Richard Steven Miller - Los Altos CA,
Mir Bahram Ghaderi - Cupertino CA,
Assignee:
Silicon Laboratories Inc. - Austin TX
International Classification:
H03K 3/00
US Classification:
331177R, 331176, 331 74, 327160, 327291
Abstract:
A frequency-control circuit, which is configured to receive a first signal having a first untuned frequency from a first oscillator, and to alter one or more pulses of the first signal to tune an output frequency of an output clock signal to have an average frequency at the desired target frequency. In some embodiments, the frequency-control circuit receives a signal from a single oscillator to generate a calibrated, precise, and temperature-stable clock.

Clock And Data Recovery Circuit For Return-To-Zero Data

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US Patent:
2003019, Oct 9, 2003
Filed:
Apr 8, 2002
Appl. No.:
10/118661
Inventors:
Roubik Gregorian - Saratoga CA,
Mir Ghaderi - Cupertino CA,
James Ho - San Jose CA,
Vincent Tso - Milpitas CA,
Assignee:
Exar Corporation - Fremont CA
International Classification:
H04L007/02
US Classification:
375/361000, 327/009000
Abstract:
A converting circuit which converts RZ data into intermeidate NRZ data. The intermediate NRZ data is then sampled to detect a phase of the intermediate NRZ data, which corresponds to the phase of the RZ data. In a preferred embodiment, the converting circuit is incorporated in a modified Hogge NRZ phase detector. A toggle flip-flop is placed in front of the Hogge phase detector. Since the toggle flip-flop is triggered by the leading edge of the RZ pulse, it essentially converts the RZ data into intermediate NRZ data. An exclusive-OR gate samples two different output stages of the Hogge NRZ phase detector, with the output stages being separated by an interim stage to provide a clock delay. The output of the exclusive-OR gate is an intermediate NRZ signal that corresponds to the input RZ data stream, which can then be sampled. The exclusive-OR gates inside the Hogge phase detector are used, as in the Hogge phase detector, to produce the up and down signals provided to a charge pump that is part of a PLL. The insertion of the toggle flip-flop allows these same exclusive-OR gates to perform the same function in the present invention.

Voltage Discharge Optimization

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US Patent:
2013022, Sep 5, 2013
Filed:
Sep 30, 2012
Appl. No.:
13/632078
Inventors:
Yafei BI - Palo Alto CA,
Mir B. GHADERI - Cupertino CA,
Wei H. YAO - Palo Alto CA,
Assignee:
APPLE INC. - Cupertino CA
International Classification:
G05F 5/00
US Classification:
323299
Abstract:
One embodiment of an apparatus to control and sense a voltage through a single node can include a comparator to monitor single node voltage, a transistor to discharge voltage through the single node and control logic. The control logic can have at least two operational phases when actively controlling the voltage through the single node. In a first phase, the control logic can configure the comparator to determine if the single node voltage is greater than a reference voltage. In a second phase, the control logic can configure the transistor to discharge voltage through the single node when the comparator has previously indicated that the single node voltage is greater than a reference voltage. The control logic can alternatively execute first and second phases to discharge the voltage to a predetermined level.

Systems And Methods For Monitoring Lcd Display Panel Resistance

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US Patent:
2014006, Mar 6, 2014
Filed:
Nov 16, 2012
Appl. No.:
13/679793
Inventors:
Yafei Bi - Palto Alto CA,
Mir B. Ghaderi - Cupertino CA,
Assignee:
APPLE INC. - Cupertino CA
International Classification:
G06F 3/044
G09G 3/36
US Classification:
345174, 345 87
Abstract:
Systems and methods for monitoring internal resistance of a display may include supplying the display via a capacitor with a first voltage and a second voltage configured to enable the display to receive touch inputs and display image data, respectively. The method may discharge the capacitor at least three times via a first resistor, a second resistor, and the first resistor and second resistor coupled in parallel with each other. The method may monitor three discharge waveforms that corresponds to when the capacitor discharges from the first voltage to the second voltage via the first resistor, the second resistor, and the first resistor and second resistor coupled in parallel with each other. Based at least in part on the discharge waveforms, the method may determine a chip on glass resistance value and a flex on glass resistance value that correspond to an internal resistance of the display.

Phase-Frequency Lock Detector

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US Patent:
5870002, Feb 9, 1999
Filed:
Jun 23, 1997
Appl. No.:
8/880656
Inventors:
Mir Bahram Ghaderi - Cupertino CA
Vincent W. S. Tso - Milpitas CA
Assignee:
Exar Corporation - Fremont CA
International Classification:
H03L 7095
US Classification:
331 17
Abstract:
A method and circuitry for detecting when a PLL achieves phase and frequency-lock to a reference frequency with minimal hardware and power dissipation are disclosed. The invention takes advantage of existing blocks within a PLL to reduce the amount of circuitry required while at the same time reducing error due to mismatch. In one embodiment, the present invention combines a coarse lock-detect circuit with a fine lock-detect circuit to achieve fast response when the input reference is lost, while filtering occasional minor phase hits due to external or internal noise.
Mir B Ghaderi from Cupertino, CA, age ~67 Get Report